Semiconductor devices are typically produced in arrays on wafer substrates ranging from 1 to 18 inches in diameter. The substrates are then separated into individual devices or dies that are packaged to allow practical macro-level connection of the devices in the context of a larger circuit. As the requirements for chip density and smaller packaging form factors increase, advances have been made in three-dimensional integration of circuits. In this technology, devices are stacked and bonded in the vertical or z-direction. Typically, the stacked devices are electrically coupled by electrical contact pads on the devices or by through-silicon vias (TSVs).
A typical process for vertically integrating devices on silicon wafers is a wafer-to-wafer integration scheme in which the host wafer and donor wafer are aligned with one another, and the wafers are bonded together using oxide-oxide fusion bonding. The donor wafer is then thinned to expose through silicon vias that connect to the host wafer, or is thinned followed by fabrication of through silicon vias that connect to the host wafer.
A long-recognized challenge in producing vertically integrated devices is reducing distortion of the wafers and wafer stack introduced during the manufacturing process. A common mechanism that introduces distortion is the disparate degrees of thermal expansion on the various components of a wafer or wafer stack. For example, the components and materials present on a wafer will typically have different coefficients of thermal expansion. At different steps of the integrated device manufacturing process, the wafers and wafer stacks will be exposed to different process temperatures, which may include thermal gradients in the wafer or wafer stack during production. Because of the different coefficients of thermal expansion, each process step taking place at a different temperature will result in differential dimensional changes between wafer components and materials, which can manifest as fixed distortion from the undistorted ideal dimensions and positions. Stresses and strains to the wafer surface may also be caused by various mechanical and chemical processes, thinning, and differences in pattern densities. Planar surface distortions between wafers may be made permanent by the bonding of the wafer surfaces.
It would be desirable to have a bonding process that reduces, eliminates, or reverses the incoming relative planar distortion between the host and donor wafer surfaces, thus improving wafer-to-wafer bonding alignment.